// ClockDivider.v - Clock Divider
//
// Input(s):
// ---------
// TODO
//
// Output(s):
// ----------
// TODO
//
// Descrip tion:
// ------------
// TODO
//
// Copyright Jabeer Ahmed and Caleb Mathisen, 2014
// 
// Created By:      Jabeer Ahmed
// Author(s) :      Jabeer Ahmed, Caleb Mathisen
// Last Modified:   TODO
//
// Revision History:
// -----------------
//
////////////////////////////////////////////////////////////////////////////////

`timescale  1 ns / 1 ns
module ClockDivider (
  //inputs
  input               clk,                      // clock    
  input       [31:0]  num_cycles,               // num cycles 
  input               set,                      // set 

  //outputs
  output reg          div_clk	= 1'b0	           // compass up-down counter 
);
  
  reg         [30:0]  h_period = 31'h0;
  reg         [31:0]  counter  = 32'h0;         // counts 1,000,000 cycles

  always @(posedge set) begin
    h_period[30:0] <= num_cycles[31:1];   
  end

  always @(posedge clk) 
  begin
    if (counter == h_period) begin
      counter <= 32'b0;                       // increment clock counter 
      div_clk <= ~div_clk;
    end 
    else begin 
      counter <= counter + 1'b1;
    end
  end

endmodule